Impact of Single pMOSFET Dielectric Degradation on NAND Circuit Performance
Document Type
Article
Publication Date
3-1-2008
Abstract
Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source-to-drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.
Publication Information
Estrada, D.; Ogas, M. L.; Southwick, R. G. III; Price, P. M.; Baker, R. J.; and Knowlton, W. B.. (2008). "Impact of Single pMOSFET Dielectric Degradation on NAND Circuit Performance". Microelectronics Reliability, 48(3), 354-363. https://doi.org/10.1016/j.microrel.2007.09.002
