Title
Electrical Continuity Testing of Through-Silicon Vias Under Static Force Application
Document Type
Student Presentation
Presentation Date
4-15-2013
Faculty Sponsor
Sarah Haight
Abstract
Through-silicon via (TSV) is a high performance interconnect technology and a new facet of advanced memory packaging which seeks to vastly improve memory density and efficiency. It employs the use of conductive vertical pillars passing through and connecting all of the stacked layers of silicon to the memory substrate. Since it is an early and contemporary technology, more information is needed about electrical and mechanical reliabilities of TSVs under conditions of environmental stress. To this end, we are developing a testing device which will provide real-time data regarding the electrical continuity of approximately 400 TSV interconnects on a prototype memory package as they are subjected to static forces. This will help facilitate identification of when and where a given interconnect failure occurs while providing comprehensive continuity data from the test. Moving forward, this data will assist in the understanding of failure causes and prove useful in adapting TSV design and implementation.