Publication Date

8-2012

Type of Culminating Activity

Thesis

Degree Title

Master of Science in Electrical Engineering

Department

Electrical and Computer Engineering

Supervisory Committee Chair

R. Jacob Baker

Abstract

Random local variation in CMOS transistors complicates characterization procedures, modeling efforts, simulation tools, and circuit design methodologies in highly scaled CMOS devices. Mismatch is not only a concern for closely matched device pairs in analog circuits; digital circuit designers also have to consider the effects of random variation. Device characterization, modeling, process development, and circuit design engineers have to work together to mitigate the impact of random local variation. This thesis outlines the primary challenges of CMOS characterization, modeling, and circuit design in the presence of random local variation and offers guidelines and solutions to help mitigate and model the unique characteristics that mismatch introduces. Random data sets are generated to demonstrate the statistical transistor and circuit response to random variation across die and process and to demonstrate the challenges in each area of CMOS development.

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