Wide Range, Low Jitter Delay-Locked Loop Using a Graduated Digital Delay Line and Phase Interpolator
Publication Date
11-2006
Type of Culminating Activity
Thesis
Degree Title
Master of Science in Engineering, Electrical Engineering
Department
Electrical and Computer Engineering
Major Advisor
R. Jacob Baker
Abstract
High-speed synchronous integrated circuits (ICs), such as microprocessors and memories, require clock signals to be tightly aligned for proper operation. Clock synchronization circuits are essential to eliminate clock skew across all process, voltage and temperature (PVT) variations. Digital delay-locked loops (DLLs) are commonly used for clock synchronization in modem ICs because of their superior stability and process portability. However, a drawback to these circuits is that a large number of delay elements are required to accomplish high performance across a wide operating range. A digital DLL suitable for use in a DDR-SDRAM is presented. The DLL has a graduated coarse delay line and a phase interpolating fine delay line, allowing it to cover the operating range and alignment requirements of all currently defined DDR-SDRAM families while reducing the number of delay elements by a factor of two over a traditional digital DLL.
Recommended Citation
Booth, Eric R., "Wide Range, Low Jitter Delay-Locked Loop Using a Graduated Digital Delay Line and Phase Interpolator" (2006). Boise State University Theses and Dissertations. 514.
https://scholarworks.boisestate.edu/td/514