Publication Date
5-2012
Type of Culminating Activity
Thesis
Degree Title
Master of Science in Electrical Engineering
Department
Electrical and Computer Engineering
Major Advisor
R. Jacob Baker
Advisor
Kristy A. Campbell
Advisor
Wan Kuang
Abstract
Resistive random access memory (RRAM) has been the topic of many research papers in recent years, as companies begin to look for non-volatile alternatives to NAND Flash. The standard testing methodologies for single devices do not work for most of the RRAM technologies, so new methods must be developed. Parasitic capacitance will destroy the device under test without current compliance circuitry. A test structure with the capability to apply current compliance in either direction was designed, simulated, and tested with electrical results. Pulses greater than 4.0 V were delivered with 100 μA current compliance, and parasitic capacitance was kept below 50 fF.
Recommended Citation
Johnson, Adam David, "Methods and Considerations for Testing Resistive Memories" (2012). Boise State University Theses and Dissertations. 257.
https://scholarworks.boisestate.edu/td/257