Publication Date

8-2023

Date of Final Oral Examination (Defense)

April 2023

Type of Culminating Activity

Thesis

Degree Title

Master of Science in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Supervisory Committee Chair

Nader Rafla, Ph.D.

Supervisory Committee Member

Benjamin Johnson, Ph.D.

Supervisory Committee Member

Jennifer Smith, Ph.D.

Abstract

Globally, there has been an increase in demand for System on Chip (SoC) applications, active medical implants, and Internet of Things (IoT) devices. However, due to challenges in the global supply chain, the design, fabrication, and testing of Integrated Circuits are often outsourced to untrusted third-party entities around the world rather than a single trusted entity. This situation presents an opportunity for adversaries to compromise the device’s integrity, performance, and functionality by inserting malicious modifications known as Hardware Trojans (HTs) into the original design. HTs can also create a backdoor in the system for malicious alterations.

The problem of hardware trojan is tackled in this thesis through the application of two types of machine learning models. The proposed methodology involves utilizing netlist features of the digital hardware design generated from synthesis and inputting them into the machine learning model. Additionally, measures are taken to prevent interdependence among features, which could lead to overfitting on the training dataset.

DOI

https://doi.org/10.18122/td.2119.boisestate

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