Publication Date
5-2011
Type of Culminating Activity
Thesis
Degree Title
Master of Science in Electrical Engineering
Department Filter
Electrical and Computer Engineering
Department
Electrical and Computer Engineering
Supervisory Committee Chair
R. Jacob Baker, Ph.D.
Abstract
Three-dimensional (3D) inductors using high aspect ratio (10:1) thru-wafer via (TWV) technology in a complementary metal oxide semiconductor (CMOS) process have been designed, fabricated, and measured. The inductors were designed using 500 μm tall vias with the number of turns ranging from 1 to 20 in both a wide and narrow trace width to space ratios. Radio frequency characterization was studied with emphasis upon de-embedding techniques and resulting effects. The open, short, thru de-embedding (OSTD) technique was used to measure all devices. The highest quality factor (Q) measured was 11.25 at 798MHz for a 1-turn device with a self-resonant frequency (fsr) of 4.4GHz. The largest inductance (L) measured was 45nH on a 20-turn wide trace device with a maximum Q of 4.25 at 732MHz. A 40% reduction in area is achieved by exploiting the TWV technology when compared to planar devices. This technology shows promising results with further development and optimization.
Recommended Citation
VanAckern, Gary, "Design Guide for CMOS Process On-Chip 3D Inductor using Thru-Wafer Vias" (2011). Boise State University Theses and Dissertations. 173.
https://scholarworks.boisestate.edu/td/173
