Development of Experimental Techniques for the Study of Negative Bias Temperature Instability in pMOSFET Devices
Dr. Bill Knowlton
Negative bias temperature instability (NBTI) is a significant reliability concern in SiO2 gate dielectric based pMOSFETs due to time and temperature-dependent fluctuations in device parameters during both on and off state operation. While NBTI effects can be observed over relatively long periods (> 1 s) and at normal operating temperatures, NBTI behavior also occurs very early (< 10 ms) during stress (on state) and recovery periods (off state). However, measurements over time periods less than 10 ms are challenging due to frequency limitations of DC electrical measurement equipment and device structures. A recent attempt to slow the kinetics of NBTI and capture earlier NBTI events using cryogenic temperatures (< 200 K) has shown promise. To address the need for measurements at the onset of stress or recovery, novel experimental techniques leveraging the advantages of fast electrical characterization methods and cryogenic temperatures will be developed. Employing fast characterization methods will allow measurements with a temporal resolution approaching 1 µs. Performing characterizations at cryogenic temperatures will take advantage of temperature dependent charge trapping kinetics, thereby moving stress and / recovery onset behavior into the measurement window. Data acquired with the developed techniques will provide the time and thermal dependence quantification needed to confirm the presence and/or dominance of one or more trapping mechanisms and to refine NBTI models. Improved understanding of the causes of NBTI could lead to its mitigation in future pMOSFET devices. The experimental techniques developed here could also be applied to other time dependent mechanisms such as positive bias temperature instability observed in nMOSFET devices with high-κ gate dielectric materials.