Real-Time Bitstream Decompression Scheme for FPGAs Reconfiguration
Document Type
Conference Proceeding
Publication Date
2018
Abstract
The state-of-the-art FPGAs require massive configuration files seeking on-chip large memory storage. Partial reconfigurable applications demand even more data storage for several additional partial bitstreams. To alleviate the memory storage requirements, bitstream compression techniques are needed. Efficient compression algorithms usually involve high complex hardware decompression circuits. This might increase the FPGA's (re)configuration time. In run-time reconfigurable applications, the required time of the decompression engine must be minimized. In this paper, we present a design and implementation of a newly developed bitstream decompression algorithm. The decompression circuit was implemented using Xilinx Vivado EDA design suite on a Zynq-based FPGA. While consuming only 118 CLB slices, 0.89% of the fabric, the decompression speed can reach the theoretical maximum reconfiguration frequency of 400 MB/s on 100 MHz clock as verified by hardware implementation. Furthermore, the effect of the FIFO buffer size and DMA configuration parameters on the decompression speed were studied.
Publication Information
Daoud, Luka; Hussein, Fady; and Rafla, Nader. (2018). "Real-Time Bitstream Decompression Scheme for FPGAs Reconfiguration". 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 1082-1085. http://dx.doi.org/10.1109/MWSCAS.2018.8624003