Title

High Level Synthesis Using Vivado HLS for Optimizations of SHA-3

Document Type

Conference Proceeding

Publication Date

2017

DOI

http://dx.doi.org/10.1109/MWSCAS.2017.8052985

Abstract

Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware design. HLS tools provide us with advanced capabilities for design evaluation and a wide variety of optimization techniques. In this paper, the SHA-3 hashing algorithm and its implementation onto a Xilinx® Zynq-7000 SoPC is explored. The SHA-3 hashing algorithm is initially coded in C programming language and then implemented with Xilinx Vivado HLS. The HLS tool enabled us to quickly analyze our design to make suitable optimizations which led to increased throughput of the SHA-3 hashing algorithm, up to 2000 Mbps. After pipelining the synthesized hardware design, it was capable of hashing a block of 1088 bits in 70 clock cycles.

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