Document Type
Conference Proceeding
Publication Date
2017
DOI
http://dx.doi.org/10.1109/MWSCAS.2017.8053126
Abstract
A CMOS synapse design is presented which can perform tunable asymmetric spike timing-dependent learning in asynchronous spiking neural networks. The overall design consists of three primary subcircuit blocks, and the operation of each is described. Pair-based Spike Timing-Dependent Plasticity (STDP) of the entire synapse is then demonstrated through simulation using the Cadence Virtuoso platform. Tuning of the STDP curve learning window and rate of synaptic weight change is possible using various control parameters. With appropriate settings, it is shown the resulting learning rule closely matches that observed in biological systems.
Copyright Statement
© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. doi: 10.1109/MWSCAS.2017.8053126
Publication Information
Ivans, Robert C.; Cantley, Kurtis D.; and Shumaker, Justin L.. (2017). "A CMOS Synapse Design Implementing Tunable Asymmetric Spike Timing-Dependent Plasticity". 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 1125-1128.