Document Type

Conference Proceeding

Publication Date

2017

DOI

http://dx.doi.org/10.1109/IJCNN.2017.7966444

Abstract

Spiking neural circuits have been designed in which the memristive synapses exhibit spike timing-dependent plasticity (STDP). STDP is a learning mechanism where synaptic weight (the strength of the connection between two neurons) depends on the timing of pre-and post-synaptic action potentials. A known capability of networks with STDP is detection of simultaneously recurring patterns within the population of afferent neurons. This work uses SPICE (simulation program with integrated circuit emphasis) to demonstrate the spatio-temporal pattern recognition (STPR) effect in networks with 25 afferent neurons. The neuron circuits are the leaky integrate-and-fire (I&F) type and implemented using extensively validated ambipolar nano-crystalline silicon (nc-Si) thin-film transistors (TFT) models. Ideal memristor synapses are driven by a nanoparticle memory thin-film transistor (np-TFT) with a short retention time attached to each neuron circuit output. This device serves to temporally modulate the conductance path from post-synaptic neurons, providing rate-based and timing-dependent learning. With this configuration, the use of a crossbar structures would also be possible, providing dense synaptic connections and potentially reduced energy consumption.

Copyright Statement

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. doi: 10.1109/IJCNN.2017.7966444

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