Document Type
Conference Proceeding
Publication Date
2015
DOI
http://dx.doi.org/10.1109/WMED.2015.7093690
Abstract
A systematic design method is applied to study and analyze the loop stability and phase noise of a type-II 3rd-order charge pump PLL. The designed PLL outputs at 12.5 GHz, which is intended to provide a clock for a silicon photonic transmitter prototype. The charge pump current and loop filter resistor are made tunable to cover process and temperature variations. The PLL is designed in a 130 nm SiGe BiCMOS process. The rms jitter of the studied PLL output is about 5 ps with a 97.7 MHz reference clock with 4.9 ps rms jitter from a 0.05 to 12.5 GHz signal generator. The total power consumption of the PLL is less than 175 mW from a 2.5 V power supply.
Copyright Statement
© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. doi: 10.1109/WMED.2015.7093690
Publication Information
Zhu, Kehan; Saxena, Vishal; Wu, Xinyu; and Balagopal, Sakkarapani. (2015). "Design Analysis of a 12.5 GHz PLL in 130 nm SiGe BiCMOS Process". 2015 IEEE Workshop on Microelectronics and Electron Devices, 1-4. http://dx.doi.org/10.1109/WMED.2015.7093690