Teaching Digital Systems Verification Methodologies Using SystemVerilog
Document Type
Conference Proceeding
Publication Date
6-26-2011
Abstract
With the growing complexity of modern digital systems and embedded system designs, the task of verification has become the key to achieving the faster time-to-market requirement for such designs. This paper describes a graduate level, Verification of Digital Systems using SystemVerilog, offered at Boise State University as a part of the Master of Science program in Computer Engineering,. This course does not only teach syntax and semantics but also coverage-driven, constrained-random, and assertion-based verification methodologies employing the advanced features of SystemVerilog to ensure that designs meet the required specifications. The course also emphasizes the practical aspects of verification methodologies through providing students with hands-on experience on commercial verification tools such as QuestaSim, the Advanced Functional Verification suite from Mentor Graphics. Course goals are explained along with course content, format, and benefits to students. The course is designed around small practical exercises to illustrate the main concepts, tools, and language usage. A mid-term and a final project are also offered that require an automated verification environment to be designed and tested on given designs.
Publication Information
Rafla, Nader I.. (2011). "Teaching Digital Systems Verification Methodologies Using SystemVerilog". 118th ASEE Annual Conference and Exposition, June 26-29, 2011, Vancouver, BC, Canada, .