Scheduling Instruction Effects for a Statically Pipelined Processor

Authors

F. Rasapour, Boise State University
G. Cook, Boise State University
G.-R. Uh, Boise State UniversityFollow

Document Type

Conference Proceeding

Publication Date

2015

DOI

https://doi.org/10.1109/CASES.2015.7324557

Abstract

Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, which simplifies hardware and enables a new level of compiler optimizations. This paper describes an effect scheduling strategy to aggressively compact instructions, which has a critical impact on code size and performance. Unique scheduling challenges include more frequent name dependences and fewer renaming opportunities due to static pipeline (SP) registers being dedicated for specific operations. We also realized the SP in a hardware implementation language (VHDL) to evaluate the real energy benefits. Despite the compiler challenges, we achieve performance, code size, and energy improvements compared to a conventional MIPS processor.

Comments

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Publication Information

Rasapour, F.; Cook, G.; and Uh, G.-R.. (2015). "Scheduling Instruction Effects for a Statically Pipelined Processor". 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 167-176.