CMOS Radio Frequency System-on-a-Chip Design & Modeling Methodology
CMOS radio frequency integrated circuits (RFIC) presents new technical challenges when built as a single system-on-a-chip (SOC). Compared to a traditional approach of mixing different integrated circuits of GaAs, Bipolar and CMOS, SOC promises benefits in integration density, operating seed, fabrication cost, and power consumption for wireless communications. This thesis presents designs and results for some CMOS RFIC components and sub-circuits, and presents important considerations of modeling and methodology for SOC. In addition, this thesis establishes an infrastructure for continuing research methodologies of CMOS RFIC, which did not exist in a written form at Boise State University previous to this thesis.