Design and Implementation of a PCI Express (PCIe) Field Programmable Gate Array (FPGA) Memory Functional Tester
Type of Culminating Activity
Master of Science in Computer Engineering
Electrical and Computer Engineering
Sin Ming Loo
The design and implementation of a PCI Express (PCIe) Field-Programmable Gate Array (FPGA) memory functional tester is described in this thesis. The purpose for building this tester was to evaluate and prototype a framework of a low-cost memory tester using off-the-shelf personal computer (PC) components and reconfigurable hardware. PCIe is the third generation computer systems input/output bus that has been widely adopted in many computer systems on the market today. With a throughput of 0.5 GBytes per second for a single lane, this technology can easily be the cost effective memory tester backplane solution. PCIe link configurations can consist of more than one lane, and up to 32 lanes. For a 32-lane PCIe link, the maximum transfer rate is 16 GBytes per second. Use of the FPGA facilitates hardware reconfiguration, which allows the system to be configured for different purposes. The major elements of the memory tester implemented in this thesis are: the PCIe bus (physical interface), PCIe soft core, device under test, and user interface software.
The work in this thesis proves that it is possible to utilize an industry standard bus (PCIe) as the system backplane of a memory device tester. The small-scale functional memory tester prototype lays a research foundation for building large-scale, full-featured memory testers based on the PCIe backplane.
Sajjapongse, Naovarat, "Design and Implementation of a PCI Express (PCIe) Field Programmable Gate Array (FPGA) Memory Functional Tester" (2007). Boise State University Theses and Dissertations. 523.