Title

Using Pipelining to Save Power in Field-Programmable Gate Arrays

Publication Date

7-2005

Type of Culminating Activity

Thesis

Degree Title

Master of Science in Computer Engineering

Department

Electrical and Computer Engineering

Major Advisor

Nader Rafla

Abstract

Reducing the logic levels in digital hardware designs can dramatically reduce power consumption of field-programmable gate arrays (FPGAs). For this thesis, logic levels were varied by applying different degrees of pipelining to five types of circuits: a parity circuit, two multipliers, an adder-based design, a sine-cosine generator, and an encryption circuit. Power was measured to an FPGA's core logic for each of the designs.

A Xilinx Spartan-3 FPGA, which features the latest 90-nm process technology, was used for the experiments. Measurements show that reducing the logic levels in a parity circuit can cut dynamic switching power by nearly a third, with no area expense. They also indicate that introducing pipeline registers can cut power by 44 percent to 83 percent in the other designs. In some cases, the reduction can be achieved with little or no area expense. In other cases, a noteworthy area tradeoff is required.

The reduction in power can be attributed to the pipeline registers' ability to curb the number of useless signal transitions, or glitches, according to the results. Such techniques can be applied to any digital logic circuit and would be especially effective in compute- intensive designs.

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