Comparative Study of VHDL Coding Styles as Applied to Finite State Machines
Type of Culminating Activity
Master of Science in Computer Engineering
Electrical and Computer Engineering
Hardware Descriptive Languages (HDL) are used for digital hardware design and provide many coding styles to accomplish the same task. State Machines, often referred to as Finite State Machines (FSM), are one of the more complex structures that the HDL designer will develop. The objective of this thesis is to evaluate different FSM coding styles and state assignment encoding types to determine their impact on performance and resource utilization when designing complex digital systems using VHDL.
In this research, three coding styles for FSMs are evaluated: Combined Single Process FSM, State Separated FSM - Combinatorial Outputs, and State Separated FSM - Registered Outputs. This research also addresses the impact of state assignment encoding on performance and resource utilization by evaluating One-Hot and Gray encoding methods.
To achieve this task, a digital system was defined, designed, implemented, and tested. This system represents a basic serial protocol exchange that employed different logic blocks including a state machine consisting of twenty individual states.
Six VHDL entities were created utilizing the Xilinx ISE tool suite. Each entity is coded using a different methodology and different state assignment encoding. To ensure the same operation performed by each of these entities, a behavioral testbench was developed and a simulation is run on all of them.
These entities were then instantiated in separate Xilinx ISE project files and subjected to a full design flow: synthesis, translate, MAP, and Place & Route. Each stage of the design flow provided reports on resource utilization and expected performance of the design. The data was then extracted from the reports and used for the evaluation
Data extracted from these reports led to the conclusion that when a One-Hot state machine assignment encoding is used, and the coding style State Separated FSM - Registered Outputs fewer resources are used, while the Combined Single Process FSM coding style had consistent performance regardless of the state assignment encoding. The performance of the three One-Hot state machine assignment encoding variants was equitable.
Davis, Brett L., "Comparative Study of VHDL Coding Styles as Applied to Finite State Machines" (2005). Boise State University Theses and Dissertations. 517.