Pattern-Based Fault Diagnosis Using an Artificial Neural Network Implemented in VHDL
Type of Culminating Activity
Master of Science in Computer Engineering
Electrical and Computer Engineering
On modem semiconductor assemblies, it is becoming increasingly common to include a built-in self-test (BIST) unit in the design which can be used to help test the assembly during manufacturing. Unfortunately, these BIST routines often provide only minimal fail data. With increasing speeds, shrinking die, and a shift to fine ball grid array (FBGA) leads on devices, replacement of faulty semiconductor chips is becoming more difficult, and therefore more costly. When incomplete test data does not clearly show which component is faulty, even more cost stands to be added if a non- faulty device is replaced first. Current best-guess fault diagnosis is likely performed with a rules-based approach which can be time-consuming and difficult to maintain.
This thesis will show that an Artificial Neural Network implemented in VHDL, using Backpropagation methods for training, can correctly diagnose most-likely failing components based on historical fault data while providing several advantages over a rules-based approach in the form of adaptability, scalability, and generality.
Gates, Corey Dean, "Pattern-Based Fault Diagnosis Using an Artificial Neural Network Implemented in VHDL" (2006). Boise State University Theses and Dissertations. 515.