Design of an Integrated Half-Cycle Delay Line Duty Cycle Corrector Delay-Locked Loop

Publication Date


Type of Culminating Activity


Degree Title

Master of Science in Electrical Engineering


Electrical and Computer Engineering

Major Advisor

R. Jacob Baker


High-speed synchronous systems require tightly controlled clock timing allowances for high performance operation. A Delay-Locked Loop (DLL) is a commonly used circuit to de-skew any variations due to process, voltage, or temperature (PVT). While a DLL will effectively align an input reference clock to an outgoing data clock, the DLL will not adjust the reference duty cycle if it is non-ideal. For this purpose a Duty Cycle Corrector (DCC) can be used in tandem with the DLL. Through the combined use of a DLL and a DCC, a high-speed system can be provided with a clock that has been both de-skewed across PVT and has a good duty cycle.

Three DCC designs are compared: the Half-Cycle Delay Line (HCDL), Open Loop (OL), and the Integrated Half-Cycle Delay Line (IHCDL). The HCDL DCC features a stable closed loop duty cycle detection and wide duty cycle range at the cost of larger layout area. The OL DCC features less stable open loop detection with the benefit of minimal forward path delay again at the cost of larger layout area. The IHCDL DCC is a hybrid design that, through the use of only a single delay line for both 0̊ and 180̊ phase generation, provides the advantages of the HCDL DCC with a substantial improvement to the required layout area.

The design of a generic DLL and the IHCDL DCC are detailed in this thesis. The performance of the IHCDL is verified through simulation. Across a range of 3 - 10 ns the IHCDL DCC corrects duty cycle to within +/- 5% of 50%. The additional lock time and power consumption of the IHCDL DCC (compared to the DLL only) are evaluated. Finally, the jitter induced by the IHCDL DCC across PVT and voltage supply variations is evaluated. Suggestions are made for the improvement of duty cycle correction.

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