Title

Indirect Feedback Compensation Technique for Multi-Stage Operational Amplifiers

Publication Date

10-2007

Type of Culminating Activity

Thesis

Degree Title

Masters of Science in Electrical Engineering

Department

Electrical and Computer Engineering

Major Advisor

R. Jacob Baker

Abstract

Introduction

To achieve high gain with continued scaling in CMOS fabrication processes, use of three-stage op-amps has become indispensable. In the progression of CMOS technology development, the supply voltage has been decreasing while the transistor threshold volt-ages do not effectively scale. Also the inherent gain available from the transistors has been decreasing with downsizing of the transistor gate length. The traditional techniques for achieving high gain by vertically stacking up (i.e. cascoding) the transistors, to achieve high gain are becoming difficult to realize in the modem sub-100nm processes as the threshold voltage doesn't scale well. Thus the paradigm of vertical cascoding of transistors needs to be replaced by the horizontal cascading in order to design op-amps in low supply voltage processes.

This thesis presents novel multi-stage topologies for singly ended as well as fully differential op-amps with the highest performance ever reported. We have also explored and comprehensively developed the indirect feedback compensation theory for the two-stage as well as the multi-stage op-amps, The proposed indirect compensated op-amps exhibit significant improvements in speed over the traditional Miller compensated op-amps and result in much smaller layout size and lower power consumption.

Contributions in this Thesis

•Indirect feedback compensation for two and higher stage op-amps have been analyzed for all known topologies. Analysis for novel indirect feedback compensation method employing split-length devices is presented. Split-length device indirect feedback compensation is useful in high speed compensation of low-voltage op-amp topologies. The split-length indirect compensation lays the foundation for the development of ultra low power and high performance multi-stage op-amps. A test chip containing the various two-stage topologies has been fabricated in a 0.5 μm CMOS process and tested for the same load conditions. The split-length indirect compensated op-amps displayed a ten times enhancement in the gain-bandwidth and four times faster transient settling compared to the traditional Miller compensated op-amp topologies. The tested performance of the op-amps is in close accordance with the simulated results as we have used a relatively long channel CMOS process where the process variations and random offsets are negligible.

•Stable and low power three-stage op-amps can also be designed by using indirect feedback compensation, in conjunction with pole-zero cancellation, to achieve excellent phase margins close to 90°. A theory for the compensation of three and multi-stage op-amps has been presented which matches well with simulations and experiments. The three-stage op-amps documented in this thesis achieve highest simulated figures-of-merit (FoMs) compared to the state-of-art and can be directly used in integrated systems to achieve higher performance. A second chip containing various three-stage singly-ended op-amps has been designed in 0.5 μm CMOS process and is presently in fabrication.

•We have presented a discussion on the impractical and incorrect multi-stage biasing schemes which are commonly found in literature. It has been demonstrated that diff-amps must be used for the internal gain stages for robust biasing of the multi-stage op-amp. The theory for three-stage op-amp design has been extended to a generalized n-stage op-amp case and can be used to build higher order multi-stage op-amps.

•Novel multi-stage fully-differential op-amp topologies are presented which amend the impractical topologies widely reported in literature. The fully differential topologies proposed in this work combine improvised biasing schemes and novel common-mode feedback techniques to obtain op-amp topologies which are robust to large offsets. The simulated performance of the fully-differential three- stage op-amps improves by at least three times in performance over the state-of- the-art. A third test chip containing numerous fully-differential op-amps has been designed in the same 0.5 μm CMOS process and is getting fabricated. The test results for all three-stage op-amps are expected to be close to the simulated performance for this process.

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