Cryogenic Characterization of Charge Trapping in MOSFET High-k Dielectrics

Document Type


Publication Date

April 2010

Faculty Sponsor

Dr. Bill Knowlton


Electron or hole carrier trapping by lattice point defects in metal oxide silicon field effect transistor (MOSFET) high-κ gate dielectrics is a substantive impediment to desired semiconductor device behavior. Trapping behavior at cryogenic temperatures can reveal the concentration and location of trapped charge as well as the nature of carrier transport in and out of the traps. A pulsed Id-Vg method at temperatures ranging from 5.8 K to 300 K was used to characterize trapping behavior and temperature dependency. Preliminary results demonstrated that trapping is dependent on temperature and pulse width. The temperature dependence may indicate the location (depth) of the traps from the silicon into the gate dielectric. The pulse-width dependence suggests that electrons leave the inversion region in the silicon to occupy traps within the gate dielectric until the traps within reach are filled. These observations imply that the ability to vary temperature and pulse timing provides a unique means to study defect-carrier kinetics. However, it was noted that while averaging multiple pulse responses significantly reduced measurement noise, the pulse duty cycle had a larger than expected effect on de-trapping between measurements, thus causing some skewing of the data. Future work will include verification that sufficient de-trapping occurs between measurements and sampling improvements to increase measurement resolution and reduce noise.

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