The bandwidth and power consumption of dynamic random access memory (DRAM), used as the main memory of a computer system, impacts computer execution rates. DRAM manufacturers focus on density increases, due to the innate price per bit decline of main memory, while processor manufacturers continually focus on boosting performance. This leads to a performance gap between the two technologies. Proximity communication promises to increase the off/on chip bandwidth of DRAM products while reducing the power consumption of the main memory system. The design of a memory system employing 4 Gb DRAM chips with a 64-bit wide communication bus using proximity communication is proposed. Technological roadblocks are analyzed and novel solutions are proposed. The proposed 4 Gb DRAM architecture can reduce the power consumption of a main memory system by 50% while increasing the bandwidth by 100%. The 4 Gb chip architecture measures 68.88 mm2 and has an array efficiency of 59.9%. The estimates are comparable to 2012 International Technology Roadmap for Semiconductors’ (ITRS) estimates of 74 mm2 and 56%, respectively.
©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. DOI: 10.1109/WMED.2010.5453754
Harvard, Qawi; Baker, R. Jacob; and Drost, Robert. (2010). "Main Memory with Proximity Communication: A Wide I/O DRAM Architecture". 2010 IEEE Workshop on Microelectronics and Electron Devices (WMED), 1-4. http://dx.doi.org/10.1109/WMED.2010.5453754