HLS Implementation of Linear Discriminant Analysis Classifier
Data classification has improved significantly over time and nowadays is used in a variety of purposes and applications. This paper demonstrates the design and implementation of multivariate classifier linear discriminant algorithm on a Field Programable Gate Array (FPGA) as System on Chip (SoC). The classifier is optimized using High Level Synthesis (HLS) techniques. The optimized design is placed on the programmable logic part of the chip while its controller is built on the embedded processor of the same chip. The paper details the process of the classifier design and optimization and reports on the power consumption, resource utilization, latency, and algorithm accuracy before and after optimization.
Wasef, Michael R. and Rafla, Nader. (2020). "HLS Implementation of Linear Discriminant Analysis Classifier". In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. https://doi.org/10.1109/ISCAS45731.2020.9181270