Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides exibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.
This document was originally published in Proceedings of 34th International Conference on Computers and Their Applications by International Society for Computers and their Applications. Copyright restrictions may apply.
Daoud, Luka; Hussein, Fady; and Rafla, Nader. (2019). "Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)". Proceedings of 34th International Conference on Computers and Their Applications, 58, 36-44.