A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and radiation testing. Fabrication and postprocessing of the memory are also discussed.
This document was originally published by IEEE in 51st Midwest Symposium on Circuits and Systems. Copyright restrictions may apply. DOI: 10.1109/MWSCAS.2008.4616863
Ande, H. K.; Busa, P.; Balasubramanian, M.; Campbell, Kristy A.; and Baker, R. Jacob. (2008). "A New Approach to the Design, Fabrication, and Testing of Chalcogenide-Based Multi-State Phase-Change Nonvolatile Memory". 51st Midwest Symposium on Circuits and Systems, 570-573. http://dx.doi.org/10.1109/MWSCAS.2008.4616863