Design of a 10-Gb/s Integrated Limiting Receiver for Silicon Photonics Interconnects

Authors

Kehan Zhu, Boise State University
Sakkarapani Balagopal, Boise State University
Vishal Saxena, Boise State UniversityFollow
Wan Kuang, Boise State University

Document Type

Article

Publication Date

8-4-2013

DOI

http://dx.doi.org/10.1109/MWSCAS.2013.6674748

Abstract

A 10-Gb/s integrated limiting receiver for silicon photonics interconnects is proposed with detailed system level and circuit level design and analysis. Silicon photonics devices fabricated in silicon-on-insulator (SOI) can be seamlessly integrated with standard CMOS process, which allows compact system integration and significantly lower power dissipation. By taking the advantages of low parasitic capacitance of the on-chip Germanium (Ge) detector and adopting bandwidth extension techniques, a total bandwidth of 7.2 GHz with 87 mW power consumption is obtained in a 0.13-μm CMOS process. The final differential output signal has a peak-to-peak swing of about 1.2 V and a peak-to-peak jitter of 14.3 ps and 9.8 ps for 10-Gb/s 2⁷ - 1 PRBS data with an average received optical power of -17 dBm and 0 dBm, respectively.

Publication Information

Zhu, Kehan; Balagopal, Sakkarapani; Saxena, Vishal; and Kuang, Wan. (2013). "Design of a 10-Gb/s Integrated Limiting Receiver for Silicon Photonics Interconnects". 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 713-716.