Document Type
Conference Proceeding
Publication Date
4-12-2013
DOI
http://dx.doi.org/10.1109/WMED.2013.6544508
Abstract
A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.
Copyright Statement
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Publication Information
Zhu, Kehan; Balagopal, Sakkarapani; and Saxena, Vishal. (2013). "Systematic Design of 10-Bit 50MS/s Pipelined ADC". 2013 IEEE Workshop on Microelectronics and Electron Devices, 17-20.