Finite State Machines (FSM), are one of the more complex structures found in almost all digital systems today. Hardware Description Languages are used for high-level digital system design. VHDL (VHSIC Hardware Description Language) provides the capability of different coding styles for FSMs. Therefore, a choice of a coding style is needed to achieve specific performance goals and to minimize resource utilization for implementation in a re-configurable computing environment such as an FPGA. This paper is a study of the tradeoffs that can be made by changing coding styles. A comparative study on three different FSM coding styles is shown to address their impact on performance and resource utilization for the most commonly used encoding methods for FPGA designs. The results show that a particular coding style leads to a savings in resource utilization with a significant performance improvement over the others while the others pose a consistent performance regardless of the resource utilization outcome.
This document was originally published by IEEE in 49th IEEE International Midwest Symposium on Circuits and Systems, 2006. Copyright restrictions may apply. DOI: 10.1109/MWSCAS.2006.382066
Rafla, Nader I. and Davis, Brett L.. (2006). "A Study of Finite State Machine Coding Styles for Implementation in FPGAs". 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, 337-341. http://dx.doi.org/10.1109/DIAL.2006.14