A 2 GHz Effective Sampling Frequency K-Delta-lSigma Analog-to-Digital Converter

Authors

Andrew Labaziewicz, Boise State University
R. Jacob Baker, Boise State UniversityFollow

Document Type

Conference Proceeding

Publication Date

8-7-2011

DOI

http://dx.doi.org/10.1109/MWSCAS.2011.6026453

Abstract

As CMOS technology scales to nanometer dimensions, analog-to-digital converter (ADC) design has become increasingly more challenging. This is mainly due to the increased transistor leakage currents, process variations, and poor matching. The K-Delta-1-Sigma (KD1S) modulator was proposed as a practical solution for designing high-speed ADCs in nanometer CMOS processes. This paper presents an 8-path KD1S modulator with an effective sampling frequency of 2 GHz derived from a 250 MHz input clock. The simulation results confirm the true first-order noise shaping of the modulator. The simulated SNR is 44.95 dB and the simulated SNDR is 44.41 dB corresponding to N_eff = 7.17 bits with a conversion bandwidth of 15.625 MHz.

Publication Information

Labaziewicz, Andrew and Baker, R. Jacob. (2011). "A 2 GHz Effective Sampling Frequency K-Delta-lSigma Analog-to-Digital Converter". 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 1-4.