Full-Feedforward K-Delta-1-Sigma Modulator

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Conference Proceeding

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This paper discusses the design of a second-order full-feedforward K-Delta-1-Sigma (KD1S) modulator with a fast feedback loop around the quantizer. The proposed second-order KD1S modulator employs inherent interleaving with shared op-amp and K-quantizing paths that has the potential to achieve significantly higher conversion bandwidths than traditional delta-sigma ADCs. A second-order full-feedforward ADC using an 8-path KD1S modulator and ideal components achieves an SNR of 70 dB (or 12-bit resolution) for a conversion bandwidth of 6.25 MHz with 800 MHz effective sampling rate. For the same bandwidth, the proposed second-order KD1S modulator is simulated in 130 nm CMOS achieving 58 dB SNR (or 10-bit resolution).

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