CMOS Image Sensor Using Delta-Sigma Modulation

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Conference Proceeding

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A CMOS image sensor ADC using delta-sigma modulation is presented and discussed. Experimental results from a test chip are presented. The experimental results show that the proposed ADC has several benefits over the use of pipeline ADCs including noise reduction, fast design times, ease with which to maximize ADC output based on a varying input range, and simple symmetric analog routing for large arrays. A clock frequency of 100 MHz, and a 20 mus row sense time results in resolutions of 10-bits. A 2000 column imager using the proposed topology can output data continuously every 10 ns after an initial one row latency.

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