K-Delta-1-Sigma Modulators for Wideband Analog-to-Digital Conversion

Author

Vishal Saxena, Boise State UniversityFollow

Publication Date

5-2010

Type of Culminating Activity

Dissertation

Degree Title

Doctor of Philosophy in Electrical and Computer Engineering

Department

Electrical and Computer Engineering

Supervisory Committee Chair

R. Jacob Baker, Ph.D.

Abstract

As CMOS technology scales, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes a first-order K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared integrator and K-quantizing feedback paths and can potentially achieve significantly higher conversion bandwidths when compared to the traditional switched-capacitor delta-sigma ADCs. The shared integrator in the KD1S modulator settles over a half the clock period and the op-amp is designed to operate at the base clock frequency.

In this dissertation, the first-order KD1S modulator topology is analyzed for the effects of the non-idealities introduced by the K-path operation of the switched-capacitor integrator. Then, the concept of KD1S modulator is extended to higher-order modulators in order to achieve superior noise-shaping performance. A systematic synthesis method has been developed to design and simulate higher-order KD1S modulators at the system level. In order to demonstrate the developed theory, a prototype second-order KD1S modulator has been designed and fabricated in a 500-nm CMOS technology. The second-order KD1S modulator exhibits wideband noise-shaping with an SNDR of 42.7 dB or 6.81 bits in resolution for K_path = 8 paths, an effective sampling rate of ƒs,new=800 MHz, effective oversampling ratio K_path•OSR=64 and a signal bandwidth of 6.25 MHz. The second-order KD1S modulator consumes an average current of 3.0 mA from the 5 V supply and occupies an area of 0.55 mm².

Recommended Citation

Saxena, Vishal, "K-Delta-1-Sigma Modulators for Wideband Analog-to-Digital Conversion" (2010). Boise State University Theses and Dissertations. 91.
https://scholarworks.boisestate.edu/td/91