Publication Date

12-2012

Type of Culminating Activity

Thesis - Boise State University Access Only

Degree Title

Master of Science in Electrical Engineering

Department

Electrical and Computer Engineering

Major Advisor

Vishal Saxena

Abstract

As the demand for new electronic products grows at a rapid pace, so does the complexity of the circuit designs implemented. This complexity is transforming designs, primarily into becoming mixed-signal in nature, by incorporating both analog and digital circuit contents; and these in turn are creating new challenges to existing design methodologies. The success of new electronic products depends largely on quick design cycles and the manufacturer’s ability to get products to the market place as quickly as possible. Consequently, there is a greater need for the development of a mixed-signal flow methodology that can handle design, integration, and verification processes within a quicker time-frame than what is currently possible.

This thesis proposes a new model for developing a mixed-signal Integrated Circuit (IC) flow methodology, within the context of the delta-sigma (ΔΣ) data converter design. The proposed flow methodology is discussed and presented in parallel with the design of a prototype 3rdorder continuous-time (CT) delta-sigma (ΔΣ) modulator. This proposal first discusses the background of the ΔΣ data converter and the specifications of the design are considered. Secondly, the system design of a discrete-time (DT) ΔΣ data modulator and its transformation to a CT-ΔΣ design are discussed and the designs are simulated to achieve the desired specifications. Using specifically designed schematic, consisting of hierarchical sub-blocks and verification plan for testing, the proposed design is then translated to a circuit design environment. The sub-blocks are realized by behavioral models and simulated for desired performance. Once the simulation results match the system simulation, the models are replaced by transistor level implementation and from this point, proceed to layout and fabrication in 0.5µm C5FN on-semi process technology.

The designed and tested prototype 3rd order CT-ΔΣ exhibits a noise-shaping with a signal-to-noise distortion ratio (SNDR) of 82 dB with a resolution of 13.32 bits in a 48 KHz bandwidth, dissipating 5.4 mW with a 5 V power supply and occupying an area of 4.5 mm2.

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