Thermal Stability of Barrier Layers for Copper Metallization

Publication Date


Type of Culminating Activity


Degree Title

Master of Science in Mechanical Engineering


Mechanical and Biomechanical Engineering

Major Advisor

Amy J. Moll


The drive for miniaturization of electronic devices has obligated the semiconductor industry to look for advanced packaging technologies. 3D packaging is one of the ways to achieve high functionality while minimizing package size. One approach to 3D technology is through the use of through-wafer interconnects (TWI), where vias provide electrical connections between the stacked layers.

The scaling down of dimensions places severe demands on the interconnect material, due to concerns with reliability and performance of the circuit. Hence, copper has replaced aluminum as the interconnect metal due to its high conductivity and superior resistance to electromigration. However, copper is a fast diffuser in silicon and exists in a dissolved state as well as in the form of precipitates within silicon, both of which degrade the device performance. A barrier is necessary to stop this copper diffusion into silicon.

Titanium nitride meets the requirement of a good barrier layer for copper diffusion and is used as the diffusion barrier in this work. Though thick barriers have lower diffusivity for copper, the high aspect ratio and complex geometry of the via require thin films to reduce its impact on via resistance. High conformality of the barrier layers is also critical to ensure viable coverage at the bottom and side walls of the via. Parylene is used as the insulating layer, which is significant in this project.

The present work develops characterization techniques for testing the thermal stability of the barrier layers for copper metallization. The need for thin diffusion barriers due to decrease in feature size has led to the examination of four different barrier schemes with two different thicknesses of TiN and two different thicknesses of Parylene. The barrier thicknesses used were 110nm/220nm of TiN and 1000nm/600nm of Parylene. The techniques employed were Electrical test method (Sheet resistance measurements), Scanning Electron Microscopy (SEM), and Energy Dispersive Spectroscopy (EDS). All four samples were examined at room temperature and after a two hour heat treatment at 250°C. Initially, determination of sheet resistance for the samples had some drawbacks and was later improved. Finally, drawbacks, conclusions, and recommendations are made on efficient barrier schemes and on techniques to be employed for detection of Cu penetration in Si.

Research on various tools for detecting the barrier failure have shown that electrical testing methods are more sensitive than most of the depth profiling techniques. The factors affecting the stability of the barrier layers, the characterization techniques useful for detecting copper penetration in silicon, and the unique properties of copper in silicon are also discussed.

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