Title

A Novel Approach to Investigate the Reliability of Titanium Nitride/Hafnium Oxide/Silicon Dioxide/Silicon Gate Stacks

Publication Date

5-2008

Type of Culminating Activity

Thesis

Degree Title

Master of Science in Electrical Engineering

Department

Electrical and Computer Engineering

Major Advisor

William B. Knowlton

Abstract

The continued reduction in gate length of metal-oxide-semiconductor (MOS) transistors has required a subsequent reduction in the effective gate oxide thickness. Silicon dioxide (SiO2) is now reaching its physical limits requiring the introduction of new high-k dielectric materials into the gate stack. Hafnium oxide (HfO2) is the most likely candidate for a new gate oxide in conjunction with a SiO2 interfacial layer. A dielectric bi-layer increases the complexity of the system with unknown affects on reliability of the devices. In this thesis, a novel approach is presented to assess and identify the location and initiation of dielectric breakdown. The method consists in varying the electrical stress across the HfO2 layer while keeping the electrical stress across the SiO2 layer constant. The proposed hypothesis is that differences in time to failure would indicate the HfO2 layer suffered dielectric breakdown first. Conversely, similar time to failure would indicate the SiO2 layer is failing.

In order to facilitate such an approach, a dual oxide energy band diagram program was developed. Using analytical equations, the energy band of a MOS device composed of two dielectric materials is visualized and simple calculations are performed. The band diagram program was used to determine the test parameters for constant-voltage-stress (CVS) at a constant electric field performed on TiN/HfO2/SiO2/Si gate stacks with HfO2 thicknesses ranging from 3-15nm. Nearly immediate dielectric breakdown prompted a more systematic approach where the breakdown strength of the TiN/HfO2/SiO2/Si gate stack was identified over various HfO2 thicknesses using ramped-voltage-stress (RVS) tests.

From the RVS tests data analysis indicates the electric field across the HfO2 at dielectric breakdown ranges from -6.5MV/cm to -2.5MV/cm as the HfO2 thickness is increased from 3nm to 15nm. The electric field across the SiO2 ranges from -19MV/cm to -8MV/cm as the HfO2 thickness increases. The voltage drop across the SiO2 interfacial layer decreases while the voltage drop across the HfO2 increases as the HfO2 thickness increases.

Energy band diagram calculated carrier transport maps show the transport mechanism at dielectric breakdown changes as the HfO2 thickness changes. Changes in the carrier transport mechanism, resulting in energy being deposited at different locations in the gate stack, may be responsible for the change in the dielectric breakdown field of HfO2/SiO2 gate stacks in the thickness range investigated. Analysis of the carrier transport maps reveals potential problems in keeping the electric field and transport regime the same over the intended range of HfO2 thicknesses. Using the results and analysis presented in this thesis, an improved experimental procedure is proposed for the novel reliability approach.

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