Investigation of Sub-50nm Non-classical CMOS Transistor Structures

Publication Date


Type of Culminating Activity


Degree Title

Master of Science in Engineering, Electrical Engineering


Electrical and Computer Engineering

Major Advisor

Stephen A. Parke


As the transistor size is reduced below Sub-50nm to achieve faster circuits and better performance, the complexity of device design increases a lot. This is because of the short-channel effects, and quantum mechanical effects, which playa major role in deciding the performance of the device. The conventional CMOS transistor cannot be scaled down to Sub-50nm. Hence novel transistor structures are investigated that could be scaled down below Sub-50nm. Many novel transistor structures like quantum dots, carbon nano-tube transistors, single electron transistors, molecular transistors, and biological transistors are being studied. But they are not compatible with the existing worldwide CMOS technology base. However much improvement in technology has to be made, in what ITRS calls as, ‘Non-classical CMOS transistor structures'.

In this work we study some of these novel structures that are already fabricated. Then the novel transistor structures that we propose are introduced. Based on these proposed novel transistor structure we have performed simulations to compare the performance between the two proposed structures. Also, these simulation results are compared to the experimental measured results of the already existing novel transistor structure. We conclude by choosing the best novel transistor structure based on their performance and then suggest any future work.

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