Title

SRAM Subthreshold Current Recovery After Unipolar AC Stressing

Document Type

Conference Proceeding

Publication Date

2004

Abstract

Standby current in a Static RAM is a measure of the subthreshold current of the transistors which make the inverter pair in the SRAM. Application of stress on the transistor gates typically causes defects in the gate oxide leading to higher leakage and higher subthreshold current. We have recently found however that an AC stress cycling on the SRAM however mduces the leakage in many cases. A trapped charge model is proposed for decrease in subtreshold current leading to lower observed standby current on continuous negative unipolar write stress. Several meohanisms have been proposed earlier such as Poole-Frenkel enhanced emission from traps, trap assisted tunneling, and band-to-band tunneling to explain possible source of off-current.1-3

As devices shrink, for low Vcc and Vt devices, subtreshold current becomes critical.4-6 Low standby current becomes vital for application like cell phones. The electronic industry is trying to find methods to reduce power consumption by reducing leakage, in addition to reducing the on current.

We have recently discovered that with application of unipolar negative AC stress on the gate of the SRAM, continuous increase in sub threshold leakage does not happen as expected as the oxide is being weakened.7-9 We have found that unless the applied stress is very high for a relatively long time the leakage current follows a periodic pattern when plotted with time. In addition to being an important finding for the application of SUM, it also gives another insight into the behavior of gate oxide with respect to charge trapping and de-trapping.

Figure I shows typical 6-transistor static RAM cell, which is used for this study. The process technology is 1.8V, 0.13 micron, single well CMOS technology with gate oxide thickness of 32 A and gate length/width of 0.15 micron/ 2 micron. The N well is biased at Vec to prevent latch-up. A single cell can be selected by accessing particular row and column. Stress is applied to transistor by writing to the cell at high voltages. During the stress (write operation) Vcc: was kept at 2.4 V and 3 V. Bit line was taken to Vcc and bit line bar was kept at Vss (ground) for 200 nS. This resulted in Vcc at the gate of P-channel transistor T2 and close to 0 V(Vss) on the P-channel transistor T1. Since the N well in which the P channel transistor is located is biased at Vcc, the effective voltage on the gate of transistor TI was -2.4V or -3V during this part of the stress. The N channel transistor T3 sees close to 0 volt (Vss) at its gate.

Write is followed by a Read operation. During the read cycle (200nS). both bit line and bit line bar are kept at Vcc/2. The gate voltage on all transistors (T1, T2, T3 and T4) therefore is Vcc/2 which is 1.5 V or 1.2 for 200nS. 1.5 V on the P channel results in an effective -1.5 V on the gate. N channel is turned on because it sees l.5V or I .2V.

Read is followed by a reverse write cycle for 200nS. During this cycle the bit line is at Vss (OV) and bit line bar is at Vcc . In this case T1 P-channel gate is going to see close to Vcc which will results in approximately 0V on the gate of TI resulting in TI turning off. The N channel transistor T3 is on during this cycle and sees close to Vcc at the gate.

Standby leakage current was measured periodically. Standby leakage current which is measured between Vcc and Vss when bit line and bit line bar are both kept at 0V. Stress was stopped to measure leakage. The duration of measurement was 5 seconds. Measurements were made at Vcc of 1.8V, 1.95 V and 2.4 V. The observation shows (Figures 3,4 and 5) that Isb may increase or decrease monotonically or may show non monotonic variations with time.