As CMOS technology shrinks, the transistor speed K-quantizing paths and can achieve significantly higher conversion bandwidths when compared to the traditional deltasigma ADCs. The 8-path KD1S modulator achieves an SNR of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25 MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies in the first test chip performance are discussed along with their alleviation to achieve theoretical performance.
Saxena, Vishal; Li, Kaijun; Zheng, Geng; and Baker, R. Jacob. (2009). "A K-Delta-1-Sigma Modulator for Wideband Analog to Digital Conversion". 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009. MWSCAS '09, 411-414. http://dx.doi.org/10.1109/MWSCAS.2009.5236069