Systems on Reconfigurable Chips contain rich resources of logic, memory, and processor cores on the same fabric. This platform is suitable for implementation of Evolvable Reconfigurable Hardware Architectures (ERHA). It is based on the idea of combining reconfigurable Field Programmable Gate Arrays (FPGA) along with genetic algorithms (GA) to perform the reconfiguration operation. This architecture is a suitable candidate for implementation of early-processing stage operators of image processing such as filtering and edge detection. However, there are still fundamental issues need to be solved regarding the on-chip reprogramming of the logic. This paper presents a framework for implementing an evolvable hardware architecture for edge detection on Xilinx Virtex–4 chip. Some preliminary results are discussed.
This document was originally published by IEEE in Midwest Symposium on Circuits and Systems, 2007. Copyright restrictions may apply. DOI: 10.1109/MWSCAS.2007.4488542
Rafla, Nader I.. (2007). "Evolvable Reconfigurable Hardware Framework for Edge Detection". Midwest Symposium on Circuits and Systems, 2007, 65-68. http://dx.doi.org/10.1109/MWSCAS.2007.4488542