As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents and device mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in nano-CMOS, the K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. This paper extends the KD1S to higher order topologies using a systematic synthesis procedure. Second and third order KD1S modulator are designed and simulated to demonstrate the synthesis method.
Saxena, Vishal and Baker, R. Jacob. (2010). "Synthesis of Higher-Order K-Delta-1-Sigma Modulators for Wideband ADCs". 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 1029-1032. http://dx.doi.org/10.1109/MWSCAS.2010.5548818