Design-to-Testing: A Low-Power, 1.25 GHz, Single-Bit Single-Loop Continuous-Time ΔΣ Modulator with 15 MHz Bandwidth and 60 dB Dynamic Range

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Continuous-time Delta-Sigma (CT-ΔΣ) analog-to-digital converters have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths >15 MHz and higher resolution of 10–14 bits. This paper presents the complete design-to-testing tutorial of a state-of-the-art high-speed single-bit CT-ΔΣ architecture and its circuit design details in 0.13 μm CMOS technology node sampling at 1.25 GS/s. The designed modulator achieves higher dynamic range of 60 dB in a wide conversion bandwidth of 15 MHz and consumes only 3.5 mW. The proposed modulator achieves a Figure of Merit of 154 fJ/level.