Document Type
Article
Publication Date
11-2015
DOI
http://dx.doi.org/10.1109/TCSII.2015.2456372
Abstract
Nano-scale resistive memories are expected to fuel dense integration of electronic synapses for large-scale neuromorphic system. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in-situ learning and computing while driving a large number of resistive synapses is desired. This work presents a novel leaky integrate-and-fire neuron design which implements the dual-mode operation of current integration and synaptic drive, with a single opamp and enables in-situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18μm CMOS technology. Measurements show neuron’s ability to drive a thousand resistive synapses, and demonstrate an in-situ associative learning. The neuron circuit occupies a small area of 0.01mm2 and has an energy-efficiency of 9.3pJ/spike/synapse.
Copyright Statement
© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. doi: 10.1109/TCSII.2015.2456372
Publication Information
Wu, Xinyu; Saxena, Vishal; Zhu, Kehan; and Balagopal, Sakkarapani. (2015). "A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning". IEEE Transactions on Circuits and Systems II: Express Briefs, 62(11), 1088-1092.