A 1 GS/s continuous-time delta-sigma modulator (CT- ΔΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- ΔΣ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- ΔΣ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.
This is an author-produced, peer-reviewed version of this article. The final publication is available at www.springerlink.com. Copyright restrictions may apply. DOI: 10.1007/s10470-013-0066-2
Balagopal, Sakkarapani; Zhu, Kehan; and Saxena, Vishal. (2014). "A 1 GS/s, 31 MHz BW, 76.3 dB Dynamic Range, 34 mW CT-ΔΣ ADC with 1.5 Cycle Quantizer Delay and Improved STF". Analog Integrated Circuits and Signal Processing, 78(2), 275-286. http://dx.doi.org/10.1007/s10470-013-0066-2