Implementation of a real-time image visualization system on a reconfigurable chip (FPGA) is proposed. The system utilizes an innovative stereoscopic image capture, processing and visualization technique. Implementation is done as a two stage process. In the first stage, the stereo pair is captured using two image sensors. The captured images are then synchronized and sent to the second stage for fusion. A controller module is developed, designed, and placed on the FPGA for this purpose. The second stage is used for reconstruction and visualization of the 3D image. An innovative technique employing dual-processor architecture on the same single FPGA is developed for this purpose. The whole system is placed on a single PCB resulting in a fast processing time and the ability to view 3D video in real-time. The system is simulated, implemented, and tested on real images. Results show that this system is a low cost solution for efficient 3D video visualization using a single chip.
This document was originally published by IEEE in Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005. Copyright restrictions may apply. DOI: 10.1109/ISSPIT.2005.1577220
Rafla, Nader I.. (2005). "Real-Time 3D Image Visualization System for Digital Video on a Single Chip". Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology, 2005, 908-911. http://dx.doi.org/10.1109/ISSPIT.2005.1577220