A 1 GS/s Continuous-time Delta-Sigma modulator (CT-ΔΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB signal-to-noise is reported in a 0.13μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT-ΔΣ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT-ΔΣM has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.
Balagopal, Sakkarapani and Saxena, Vishal. (2012). "A 1 GS/s, 31 MHz BW, 76.3 dB Dynamic Range, 34 mW CT-ΔΣ ADC with 1.5 Cycle Quantizer Delay and Improved STF". 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 802-805. http://dx.doi.org/10.1109/MWSCAS.2012.6292142