Continuous-time delta sigma (CT-ΔΣ) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of ΔΣ ADCs. We proposed using two-step quantizer in a single-loop CT-ΔΣ modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing the design technique through a 130n CMOS implementation. The proposed 640 MS/s, 4th order continuous-time delta sigma modulator (CT-ΔΣM) incorporates a two-step 5-bit quantizer, consisting of only 13 comparators. The CT-ΔΣM achieves a dynamic range of 70 dB, peak SNDR of 65.3 dB with 32 MHz bandwidth (OSR = 10) while consuming only 30 mW from the 1.2 V supply. The relevant design trade offs have been discussed and presented with simulation results.
Balagopal, Sakkarapani and Saxena, Vishal. (2012). "Design of Wideband Continuous-Time ΔΣ ADCs Using Two-Step Quantizers". IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 386-389. http://dx.doi.org/10.1109/MWSCAS.2012.6292038