Document Type

Conference Proceeding

Publication Date



Continuous-time delta sigma (CT-ΔΣ) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of ΔΣ ADCs. We proposed using two-step quantizer in a single-loop CT-ΔΣ modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing the design technique through a 130n CMOS implementation. The proposed 640 MS/s, 4th order continuous-time delta sigma modulator (CT-ΔΣM) incorporates a two-step 5-bit quantizer, consisting of only 13 comparators. The CT-ΔΣM achieves a dynamic range of 70 dB, peak SNDR of 65.3 dB with 32 MHz bandwidth (OSR = 10) while consuming only 30 mW from the 1.2 V supply. The relevant design trade offs have been discussed and presented with simulation results.

Copyright Statement

© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. DOI: 10.1109/MWSCAS.2012.6292038