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The design considerations for low-power continuous time (CT) delta-sigma (ΔΣ) modulators is studied and circuit design details for a 13.5 bit modulator are given. The converter has been designed in a 0.5 um C5FN AMI CMOS technology and achieves a maximum signal-to-noise ratio (SNR) of 85 dB in a 48 kHz bandwidth and dissipates 5.4 mW from a 5 V supply when clocked at 6.144 MHz. It features a third-order active-RC loop filter, a 4-bit flash quantizer along with a Data Weighted averaging (DWA). The loop filter architecture and its coefficients have been targeted for the minimum power dissipation. The DWA also has been implemented by standard cell based synthesis to further optimize power. The figure of merit (FoM) of the CT-ΔΣ modulator is 3.71 pJ/bit. The fabricated chip of the modulator occupies an area of 4.5 mm2.


© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. DOI: 10.1109/WMED.2012.6202620