A design methodology for synthesizing power-optimized decimation filters for wideband Delta Sigma (ΔΣ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuous-time ΔΣ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45 nm CMOS technology occupies a layout area of 0.12 mm2 and consumes 8 mW power from the 1.1 V supply.
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. DOI: 10.1109/SOCC.2011.6085120
Koppula, Rajaram Mohan Roy; Balagopal, Sakkarapani; and Saxena, Vishal. (2011). "Efficient Design and Synthesis of Decimation Filters for Wideband Delta-Sigma ADCs". 2011 IEEE International SOC Conference (SOCC), 380-385. http://dx.doi.org/10.1109/SOCC.2011.6085120